1. Field of the Invention
The present invention relates to synchronous semiconductor memory devices, and more particularly, to the structure of a redundant circuit in a synchronous semiconductor memory device.
2. Description of the Background Art
In order to comply with the higher operation speed of recent microprocessors (referred to as MPU hereinafter), a synchronous DRAM (referred to as SDRAM hereinafter) is used that operates in synchronization with a clock signal to realize high speed access of a dynamic random access memory (referred to as DRAM hereinafter) employed as a main storage device. Control of the internal operation of such SDRAMs is carried out with the row related operation and the column related operation separated from each other.
In order to further increase the operation speed in a SDRAM, a bank structure is employed in which the memory cell array is divided into a plurality of banks that can operate independent of each other. In other words, the row related operation and the column related operation are controlled independently for each bank.
Each of such banks is often divided into blocks called a memory cell array mat in which are provided a sense amplifier and the like to amplify data from a selected memory cell via a bit line pair.
In order to improve the fabrication yield and the like of the SDRAM having the above structure, the so-called redundancy replacement is generally carried out where a memory cell row or memory cell column including defection is replaced with a redundant row or column that is prepared in advance.
This redundancy replacement is generally carried out on the basis of the range of the memory cell array mat where the above-described operation is activated.
In this case, the range of memory cells that can be replaced with one redundant row (or one redundant column) will be limited to this memory cell array mat range. There is a problem that the area penalty is increased by incorporating any extra redundant row (column), or that the repair efficiency by redundancy replacement is reduced.
In a SDRAM that must carry out operation at high speed, there was a problem that a sufficient operational margin could not be obtained when redundancy replacement is carried out since extra time is necessary to determine whether or not to effect redundancy replacement with respect to an externally applied address signal.
There was also a problem that the operating current and power consumption during standby are increased in accordance with a larger storage capacity of the memory.